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april 2011 dsc-5294/07 1 ?2011 integrated device technology, inc. pin description summary description the idt71v2546 is a 3.3v high-speed 4,718,592-bit (4.5 megabit) synchronous sram. it is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. thus, they have been given the name zbt tm , or zero bus turnaround. features 128k x 36 memory configurations supports high performance system speed - 150 mhz (3.8 ns clock-to-data access) zbt tm feature - no dead cycles between write and read cycles internally synchronized output buffer enable eliminates the need to control oe single r/ w (read/write) control pin positive clock-edge triggered address, data, and control signal registers for fully pipelined applications 4-word burst capability (interleaved or linear) individual byte write ( bw 1 - bw 4 ) control (may tie active) three chip enables for simple depth expansion 3.3v power supply (5%), 2.5v i/o supply (v ddq) packaged in a jedec standard 100-pin plastic thin quad flatpack (tqfp) and 119 ball grid array (bga) idt71v2546s/xs 128k x 36 3.3v synchronous zbt? sram 2.5v i/o, burst counter pipelined outputs address and control signals are applied to the sram during one clock cycle, and two cycles later the associated data cycle occurs, be it read or write. the idt71v2546 contains data i/o, address and control signal registers. output enable is the only asynchronous signal and can be used to disable the outputs at any given time. a clock enable ( cen ) pin allows operation of the idt71v2546 to be suspended as long as necessary. all synchronous inputs are ignored when ( cen ) is high and the internal device registers will hold their previous values. there are three chip enable pins ( ce 1 , ce 2 , ce 2 ) that allow the user to deselect the device when desired. if any one of these three are not asserted when adv/ ld is low, no new memory operation can be initiated. however, any pending data transfers (reads or writes) will be completed. the data bus will tri-state two cycles after chip is deselected or a write is initiated. the idt71v2546 has an on-chip burst counter. in the burst mode, the idt71v2546 can provide four cycles of data for a single address presented to the sram. the order of the burst sequence is defined by the lbo input pin. the lbo pin selects between linear and interleaved burst sequence. the adv/ ld signal is used to load a new external address (adv/ ld = low) or increment the internal burst counter (adv/ ld = high). the idt71v2546 sram utilize idt's latest high-performance cmos process and is packaged in a jedec standard 14mm x 20mm 100-pin thin plastic quad flatpack (tqfp) as well as a 119 ball grid array (bga). a 0 a - 6 1 s t u p n i s s e r d d a t u p n is u o n o r h c n y s e c 1 e c , 2 , e c 2 s e l b a n e p i h c t u p n is u o n o r h c n y s e o e l b a n e t u p t u o t u p n is u o n o r h c n y s a / r w l a n g i s e t i r w / d a e r t u p n is u o n o r h c n y s n e c e l b a n e k c o l c t u p n is u o n o r h c n y s w b 1 , w b 2 , w b 3 , w b 4 s t c e l e s e t i r w e t y b l a u d i v i d n i t u p n is u o n o r h c n y s k l ck c o l c t u p n ia / n / v d a d l s s e r d d a w e n d a o l / s s e r d d a t s r u b e c n a v d a t u p n is u o n o r h c n y s o b l r e d r o t s r u b d e v a e l r e t n i / r a e n i l t u p n ic i t a t s z ze d o m p e e l s t u p n is u o n o r h c n y s o / i 0 o / i - 1 3 o / i , 1 p o / i - 4 p t u p t u o / t u p n i a t a d o / is u o n o r h c n y s v d d v , q d d r e w o p o / i , r e w o p e r o c y l p p u sc i t a t s v s s d n u o r g y l p p u sc i t a t s 1 0 l b t 4 9 2 5
6.42 2 idt71v2546, 128k x 36, 3.3v synchronous zbt? sram with 2.5v i/o, burst counter, and pipelined outputs commercial and industria l temperature ranges pin definitions (1) note: 1. all synchronous inputs must meet specified setup and hold times with respect to clk. l o b m y sn o i t c n u f n i po / ie v i t c an o i t p i r c s e d a 0 a - 6 1 s t u p n i s s e r d d aia / n , k l c f o e g d e g n i s i r e h t f o n o i t a n i b m o c a y b d e r e g g i r t s i r e t s i g e r s s e r d d a e h t . s t u p n i s s e r d d a s u o n o r h c n y s / v d a d l , w o l n e c . s e l b a n e p i h c e u r t d n a , w o l / v d a d l d a o l / e c n a v d aia / n/ v d a d l t i n e h w l o r t n o c d n a s s e r d d a w e n h t i w s r e t s i g e r l a n r e t n i e h t d a o l o t d e s u s i t a h t t u p n i s u o n o r h c n y s a s i / v d a n e h w . d e t c e l e s p i h c e h t h t i w k c o l c f o e g d e g n i s i r e h t t a w o l d e l p m a s s i d l p i h c e h t h t i w w o l s i / v d a n e h w . d e t a n i m r e t s i s s e r g o r p n i t s r u b y n a , d e t c e l e s e d d l r e t n u o c t s r u b l a n r e t n i e h t n e h t h g i h d e l p m a s s i / v d a n e h w d e r o n g i e r a s e s s e r d d a l a n r e t x e e h t . s s e r g o r p n i s a w t a h t t s r u b y n a r o f d e c n a v d a s i d l d e l p m a s s i . h g i h / r w e t i r w / d a e ria / n/ r w e t i r w r o d a e r a s i d e t a i t i n i e l c y c d a o l t n e r r u c e h t r e h t e h w s e i f i t n e d i t a h t t u p n i s u o n o r h c n y s a s i l a n g i s . r e t a l s e l c y c k c o l c o w t e c a l p s e k a t e l c y c t n e r r u c e h t r o f y t i v i t c a s u b a t a d e h t . y a r r a y r o m e m e h t o t s s e c c a n e c e l b a n e k c o l ciw o ln e h w . t u p n i e l b a n e k c o l c s u o n o r h c n y s n e c k c o l c g n i d u l c n i , s t u p n i s u o n o r h c n y s r e h t o l l a , h g i h d e l p m a s s i f o t c e f f e e h t . d e g n a h c n u n i a m e r s t u p t u o d n a d e r o n g i e r a n e c e h t f i s a s i s t u p t u o e c i v e d e h t n o h g i h d e l p m a s , n o i t a r e p o l a m r o n r o f . r u c c o t o n d i d n o i t i s n a r t k c o l c h g i h o t w o l n e c f o e g d e g n i s i r t a w o l d e l p m a s e b t s u m . k c o l c w b 1 - w b 4 e t y b l a u d i v i d n i s e l b a n e e t i r w iw o l s e l c y c e t i r w d a o l n o . e l b a n e e t i r w e t y b w o l e v i t c a n w o s t i s a h e t y b t i b - 9 h c a e . s e l b a n e e t i r w e t y b s u o n o r h c n y s / r n e h w ( w / v d a d n a d l ( l a n g i s e t i r w e t y b e t a i r p o r p p a e h t ) w o l d e l p m a s e r a w b 1 - w b 4 e h t . d i l a v e b t s u m ) / r n e h w d e r o n g i e r a s l a n g i s e t i r w e t y b . e t i r w t s r u b a f o e l c y c h c a e n o d i l a v e b o s l a t s u m l a n g i s e t i r w e t y b w s i . r e t a l s e l c y c o w t e c i v e d e h t o t n i n e t t i r w e r a a t a d f o ) s ( e t y b e t a i r p o r p p a e h t . h g i h d e l p m a s w b 1 - w b 4 e b l l a n a c . d r o w t i b - 6 3 e r i t n e e h t o t e t i r w g n i o d s y a w l a f i w o l d e i t e c 1 , e c 2 s e l b a n e p i h ciw o l. e l b a n e p i h c w o l e v i t c a s u o n o r h c n y s e c 1 d n a e c 2 h t i w d e s u e r ae c 2 ( . 6 4 5 2 v 1 7 t d i e h t e l b a n e o t e c 1 r o e c 2 e c r o h g i h d e l p m a s 2 / v d a d n a ) w o l d e l p m a s d l e h t . e l c y c t c e l e s e d a s e t a i t i n i , k c o l c f o e g d e g n i s i r e h t t a w o l t b z m t . d e t a i t i n i s i t c e l e s e d r e t f a s e l c y c k c o l c o w t e t a t s - i r t l l i w s u b a t a d e h t , . e . i , t c e l e s e d e l c y c o w t a s a h e c 2 e l b a n e p i h cih g i he c . e l b a n e p i h c h g i h e v i t c a s u o n o r h c n y s 2 h t i w d e s u s i e c 1 d n a e c 2 e c . p i h c e h t e l b a n e o t 2 d e t r e v n i s a h o t l a c i t n e d i e s i w r e h t o t u b y t i r a l o p e c 1 d n a e c 2 . k l ck c o l cia / nr o f t p e c x e . 6 4 5 2 v 1 7 t d i e h t o t t u p n i k c o l c e h t s i s i h t e o h t i w e d a m e r a e c i v e d e h t r o f s e c n e r e f e r g n i m i t l l a , . k l c f o e g d e g n i s i r e h t o t t c e p s e r o / i 0 o / i - 1 3 o / i 1 p o / i - 4 p t u p t u o / t u p n i a t a do / ia / n d n a d e r e t s i g e r e r a h t a p t u p t u o a t a d d n a h t a p t u p n i a t a d e h t h t o b . s n i p ) o / i ( t u p t u o / t u p n i a t a d s u o n o r h c n y s . k l c f o e g d e g n i s i r e h t y b d e r e g g i r t o b l r e d r o t s r u b r a e n i liw o ln e h w . t u p n i n o i t c e l e s r e d r o t s r u b o b l n e h w . d e t c e l e s s i e c n e u q e s t s r u b d e v a e l r e t n i e h t h g i h s i o b l w o l s i . d e t c e l e s s i e c n e u q e s t s r u b r a e n i l e h t o b l . n o i t a r e p o e c i v e d g n i r u d e g n a h c t o n t s u m t i d n a t u p n i c i t a t s a s i e o e l b a n e t u p t u oiw o l. e l b a n e t u p t u o s u o n o r h c n y s a e o n e h w . 6 4 5 2 v 1 7 t d i e h t m o r f a t a d d a e r o t w o l e b t s u m e o s n i p o / i e h t h g i h s i . e t a t s e c n a d e p m i - h g i h a n i e r a e o l a m r o n n i . s e l c y c e t i r w d n a d a e r r o f d e l l o r t n o c y l e v i t c a e b o t d e e n t o n s e o d , n o i t a r e p o e o . w o l d e i t e b n a c z ze d o m p e e l sih g i h s t i o t 6 4 5 2 v 1 7 t d i e h t n w o d r e w o p d n a y l l a n r e t n i k l c e h t e t a g l l i w h g i h z z . t u p n i e d o m p e e l s s u o n o r h c n y s l a n r e t n i n a s a h n i p s i h t . e d o m p e e l s n i d e e t n a r a u g s i n o i t n e t e r a t a d . l e v e l n o i t p m u s n o c r e w o p t s e w o l . n w o d l l u p v d d y l p p u s r e w o pa / na / n. y l p p u s r e w o p e r o c v 3 . 3 v q d d y l p p u s r e w o pa / na / n. y l p p u s o / i v 5 . 2 v s s d n u o r ga / na / n. d n u o r g 2 0 l b t 4 9 2 5
6.42 idt71v2546 128k x 36, 3.3v synchronous zbt? sram with 2.5v i/o, burst counter, and pipelined outputs commercial and industri al temperature ranges 3 functional block diagram clk dq dq dq address a [0:16] control logic address control di do input register 5294 drw 01a clock data i/o [0:31], i/o p[1:4] d q clk output register mux sel gate o e c e 1, ce2, c e 2 r/ w c e n adv/ l d b w x l b o 128kx36 bit memory array recommended dc operating conditions notes: 1. v il (min.) = ?1.0v for pulse width less than t cyc /2, once per cycle. 2. v ih (max.) = +6.0v for pulse width less than t cyc /2, once per cycle. l o b m y sr e t e m a r a p. n i m. p y t. x a mt i n u v d d e g a t l o v y l p p u s e r o c5 3 1 . 33 . 35 6 4 . 3v v q d d e g a t l o v y l p p u s o / i5 7 3 . 25 . 25 2 6 . 2v v s s e g a t l o v y l p p u s000v v h i s t u p n i - e g a t l o v h g i h t u p n i7 . 1 _ _ _ _ v d d 3 . 0 +v v h i e g a t l o v h g i h t u p n i-o / i7 . 1 _ _ _ _ v q d d 3 . 0 + ) 2 ( v v l i e g a t l o v w o l t u p n i3 . 0 - ) 1 ( _ _ _ _ 7 . 0v 3 0 l b t 4 9 2 5
6.42 4 idt71v2546, 128k x 36, 3.3v synchronous zbt? sram with 2.5v i/o, burst counter, and pipelined outputs commercial and industria l temperature ranges recommended operating temperature and supply voltage pin configuration ? 128k x 36 notes: 1. pins 14, 16 and 66 do not have to be connected directly to v dd as long as the input voltage is v ih . 2. pins 83 and 84 are reserved for future 8m and 16m respectively. 3. pin 64 does not have to be connected directly to v ss as long as the input voltage is v il ; on the latest die revision this pin supports zz (sleep mode). top view 100 tqfp 100 99 98 97 96 95 94 93 92 91 90 87 86 85 84 83 82 81 89 88 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 a 6 a 7 ce 1 ce 2 bw 4 bw 3 bw 2 bw 1 ce 2 v dd v ss clk r/ w cen oe adv/ ld nc (2) nc (2) a 8 a 9 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 nc lb o a 14 a 13 a 12 a 11 a 10 v dd v ss a 0 a 1 a 2 a 3 a 4 a 5 i/o 31 i/o 30 v ddq v ss i/o 29 i/o 28 i/o 27 i/o 26 v ss v ddq i/o 25 i/o 24 v ss v dd i/o 23 i/o 22 v ddq v ss i/o 21 i/o 20 i/o 19 i/o 18 v ss v ddq i/o 17 i/o 16 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 i/o 14 v ddq v ss i/o 13 i/o 12 i/o 11 i/o 10 v ss v ddq i/o 9 i/o 8 v ss v dd i/o 7 i/o 6 v ddq v ss i/o 5 i/o 4 i/o 3 i/o 2 v ss v ddq i/o 1 i/o 0 5294 drw 02 v dd (1) i/o 15 i/o p3 v dd (1) i/o p4 a 15 a 16 i/o p1 v dd (1) i/o p2 v ss/zz (3) , nc nc nc e d a r ge r u t a r e p m e t ) 1 ( v s s v d d v q d d l a i c r e m m o cc 0 7 + o t c 0v 0% 5 v 3 . 3% 5 v 5 . 2 l a i r t s u d n ic 5 8 + o t c 0 4 -v 0% 5 v 3 . 3% 5 v 5 . 2 5 0 l b t 4 9 2 5 note: 1. t a is the "instant on" case temperature.
6.42 idt71v2546 128k x 36, 3.3v synchronous zbt? sram with 2.5v i/o, burst counter, and pipelined outputs commercial and industri al temperature ranges 5 absolute maximum ratings (1) 119 bga capacitance (1) (t a = +25 c, f = 1.0mhz) notes: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. v dd terminals only. 3. v ddq terminals only. 4. input terminals only. 5. i/o terminals only. 6. this is a steady-state dc parameter that applies after the power supply has reached its nominal operating value. power sequencing is not necessary; however, the voltage on any input or i/o pin cannot exceed v ddq during power supply ramp up. 7. t a is the "instant on" case temperature. l o b m y sg n i t a r & l a i c r e m m o c s e u l a v l a i r t s u d n i t i n u v m r e t ) 2 ( h t i w e g a t l o v l a n i m r e t d n g o t t c e p s e r 6 . 4 + o t 5 . 0 -v v m r e t ) 6 , 3 ( h t i w e g a t l o v l a n i m r e t d n g o t t c e p s e r v o t 5 . 0 - d d v v m r e t ) 6 , 4 ( h t i w e g a t l o v l a n i m r e t d n g o t t c e p s e r v o t 5 . 0 - d d 5 . 0 +v v m r e t ) 6 , 5 ( h t i w e g a t l o v l a n i m r e t d n g o t t c e p s e r v o t 5 . 0 - q d d 5 . 0 +v t a ) 7 ( l a i c r e m m o c e r u t a r e p m e t g n i t a r e p o 0 7 + o t 0 - o c l a i r t s u d n i e r u t a r e p m e t g n i t a r e p o 5 8 + o t 0 4 - o c t s a i b e r u t a r e p m e t s a i b r e d n u 5 2 1 + o t 5 5 - o c t g t s e g a r o t s e r u t a r e p m e t 5 2 1 + o t 5 5 - o c p t n o i t a p i s s i d r e w o p0 . 2w i t u o t n e r r u c t u p t u o c d0 5a m 6 0 l b t 4 9 2 5 l o b m y sr e t e m a r a p ) 1 ( s n o i t i d n o c. x a mt i n u c n i e c n a t i c a p a c t u p n iv n i v d 3 =5f p c o / i e c n a t i c a p a c o / iv t u o v d 3 =7f p 7 0 l b t 4 9 2 5 100 tqfp capacitance (1) (t a = +25 c, f = 1.0mhz) l o b m y sr e t e m a r a p ) 1 ( s n o i t i d n o c. x a mt i n u c n i e c n a t i c a p a c t u p n iv n i v d 3 =7f p c o / i e c n a t i c a p a c o / iv t u o v d 3 =7f p a 7 0 l b t 4 9 2 5 note: 1. this parameter is guaranteed by device characterization, but not production tested. note: 1. this parameter is guaranteed by device characterization, but not production tested.
6.42 6 idt71v2546, 128k x 36, 3.3v synchronous zbt? sram with 2.5v i/o, burst counter, and pipelined outputs commercial and industria l temperature ranges 1234567 a v ddq a 6 a 4 a 8 a 16 v ddq b nc ce 2 a 3 adv/ ld a 9 ce 2 nc c a 7 a 2 v dd a 12 a 15 nc d i/o 16 i/o p3 v ss nc v ss i/o p2 i/o 15 e i/o 17 i/o 18 v ss v ss i/o 13 i/o 14 f v ddq i/o 19 v ss oe v ss i/o 12 v ddq g i/o 20 i/o 21 bw 3 bw 2 i/o 11 i/o 10 h i/o 22 i/o 23 v ss r/ w v ss i/o 9 i/o 8 j v ddq v dd v dd v dd v ddq k i/o 24 i/o 26 v ss clk v ss i/o 6 i/o 7 l i/o 25 i/o 27 bw 4 nc bw 1 i/o 4 i/o 5 m v ddq i/o 28 v ss cen v ss i/o 3 v ddq n i/o 29 i/o 30 v ss a 1 v ss i/o 2 i/o 1 p i/o 31 i/o p4 v ss a 0 v ss i/o 0 i/o p1 r nc a 5 lb o v dd a 13 t nc nc a 10 a 11 a 14 nc nc/zz (3) u v ddq nc v ddq 5294 drw 13a v dd(1) nc nc(2) ce 1 nc(2) v dd(1) v dd(1) , nc nc nc nc nc pin configuration ? 128k x 36, 119 bga top view notes: 1. j3, j5, and r5 do not have to be directly connected to v dd as long as the input voltage is v ih . 2. g4 and a4 are reserved for future 8m and 16m respectively. 3. pin t7 supports zz (sleep mode) on the latest die revision.
6.42 idt71v2546 128k x 36, 3.3v synchronous zbt? sram with 2.5v i/o, burst counter, and pipelined outputs commercial and industri al temperature ranges 7 synchronous truth table (1) partial truth table for writes (1) notes: 1. l = v il , h = v ih , x = don?t care. 2. when adv/ ld signal is sampled high, the internal burst counter is incremented. the r/ w signal is ignored when the counter is advanced. therefore the nature of the burst cycle (read or write) is determined by the status of the r/ w signal when the first address is loaded at the beginning of the burst cycle. 3. deselect cycle is initiated when either ( ce 1 , or ce 2 is sampled high or ce 2 is sampled low) and adv/ ld is sampled low at rising edge of clock. the data bus will tri-state two cycles after deselect is initiated. 4. when cen is sampled high at the rising edge of clock, that clock edge is blocked from propogating through the part. the state of all th e internal registers and the i/ os remains unchanged. 5. to select the chip requires ce 1 = l, ce 2 = l, ce 2 = h on these chip enables. chip is deselected if any one of the chip enables is false. 6. device outputs are ensured to be in high-z after the first rising edge of clock upon power-up. 7. q - data read from the device, d - data written to the device. notes: 1. l = v il , h = v ih , x = don?t care. 2. multiple bytes may be selected during the same cycle. n e c / r w p i h c ) 5 ( e l b a n e / v d a d l w b x s s e r d d a d e s u e l c y c s u o i v e r pe l c y c t n e r r u co / i ) 6 ( ) r e t a l s e l c y c 2 ( ll t c e l e sld i l a vl a n r e t x ex e t i r w d a o ld ) 7 ( lh t c e l e slx l a n r e t x ex d a e r d a o lq ) 7 ( lx x h d i l a vl a n r e t n i/ e t i r w d a o l e t i r w t s r u b e t i r w t s r u b ) r e t n u o c t s r u b e c n a v d a ( ) 2 ( d ) 7 ( lx x h x l a n r e t n i/ d a e r d a o l d a e r t s r u b d a e r t s r u b ) r e t n u o c t s r u b e c n a v d a ( ) 2 ( q ) 7 ( lx t c e l e s e dlxx x p o t s r o t c e l e s e d ) 3 ( z i h lx x h x x p o o n / t c e l e s e dp o o nz i h hx x x x x x d n e p s u s ) 4 ( e u l a v s u o i v e r p 8 0 l b t 4 9 2 5 n o i t a r e p o/ r w w b 1 w b 2 w b 3 w b 4 d a e r hxxxx s e t y b l l a e t i r w lllll o / i , ] 7 : 0 [ o / i ( 1 e t y b e t i r w 1 p ) ) 2 ( l l hhh o / i , ] 5 1 : 8 [ o / i ( 2 e t y b e t i r w 2 p ) ) 2 ( lhlhh o / i , ] 3 2 : 6 1 [ o / i ( 3 e t y b e t i r w 3 p ) ) 2 ( lhhlh o / i , ] 1 3 : 4 2 [ o / i ( 4 e t y b e t i r w 4 p ) ) 2 ( l hhhl e t i r w o n l hhhh 9 0 l b t 4 9 2 5
6.42 8 idt71v2546, 128k x 36, 3.3v synchronous zbt? sram with 2.5v i/o, burst counter, and pipelined outputs commercial and industria l temperature ranges linear burst sequence table ( lbo =v ss ) interleaved burst sequence table ( lbo =v dd ) functional timing diagram (1) notes: 1. this assumes cen , ce 1 , ce 2 , ce 2 are all true. 2. all address, control and data_in are only required to meet set-up and hold time with respect to the rising edge of clock. da ta_out is valid after a clock-to-data delay from the rising edge of clock. note: 1. upon completion of the burst sequence the counter wraps around to its initial state and continues counting. note: 1. upon completion of the burst sequence the counter wraps around to its initial state and continues counting. n+29 a29 c29 d/q27 address (2) (a0 - a16) control (2) (r/ w , adv/ ld , bw x) data (2) i/o [0:31], i/o p[1:4] cycle clock n+30 a30 c30 d/q28 n+31 a31 c31 d/q29 n+32 a32 c32 d/q30 n+33 a33 c33 d/q31 n+34 a34 c34 d/q32 n+35 a35 c35 d/q33 n+36 a36 c36 d/q34 n+37 a37 c37 d/q35 5294 drw 03 , 1 e c n e u q e s2 e c n e u q e s3 e c n e u q e s4 e c n e u q e s 1 a0 a1 a0 a1 a0 a1 a0 a s s e r d d a t s r i f 00011011 s s e r d d a d n o c e s01101100 s s e r d d a d r i h t 10110001 s s e r d d a h t r u o f ) 1 ( 11000110 1 1 l b t 4 9 2 5 1 e c n e u q e s2 e c n e u q e s3 e c n e u q e s4 e c n e u q e s 1 a0 a1 a0 a1 a0 a1 a0 a s s e r d d a t s r i f 00011011 s s e r d d a d n o c e s 01001110 s s e r d d a d r i h t 10110001 s s e r d d a h t r u o f ) 1 ( 11100100 0 1 l b t 4 9 2 5
6.42 idt71v2546 128k x 36, 3.3v synchronous zbt? sram with 2.5v i/o, burst counter, and pipelined outputs commercial and industri al temperature ranges 9 notes: 1. h = high; l = low; x = don?t care; z = high impedance. 2. ce = l is defined as ce 1 = l, ce 2 = l and ce 2 = h. ce = h is defined as ce 1 = h, ce 2 = h or ce 2 = l. read operation (1) device operation - showing mixed load, burst, deselect and noop cycles (2) notes: 1. ce = l is defined as ce 1 = l, ce 2 = l and ce 2 = h. ce = h is defined as ce 1 = h, ce 2 = h or ce 2 = l. 2. h = high; l = low; x = don?t care; z = high impedance. e l c y cs s e r d d a/ r w / v d a d l e c ) 1 ( n e cw b x e o o / is t n e m m o c na 0 h l llxxx d a e r d a o l 1 + n x x h xlxxx d a e r t s r u b 2 + na 1 hl llxlq 0 d a e r d a o l 3 + nxxlhlxlq 1 + 0 p o t s r o t c e l e s e d 4 + n x x h xlxlq 1 p o o n 5 + na 2 hl llxxz d a e r d a o l 6 + nxxhxlxxz d a e r t s r u b 7 + nxxlhlxlq 2 p o t s r o t c e l e s e d 8 + na 3 l l llllq 1 + 2 e t i r w d a o l 9 + nxxhxllxz e t i r w t s r u b 0 1 + na 4 l l lllxd 3 e t i r w d a o l 1 1 + nxxlhlxxd 1 + 3 p o t s r o t c e l e s e d 2 1 + nxxhxlxxd 4 p o o n 3 1 + na 5 l l lllxz e t i r w d a o l 4 1 + na 6 hl llxxz d a e r d a o l 5 1 + na 7 l l lllxd 5 e t i r w d a o l 6 1 + n x x h xlllq 6 e t i r w t s r u b 7 1 + na 8 hl llxxd 7 d a e r d a o l 8 1 + nxxhxlxxd 1 + 7 d a e r t s r u b 9 1 + na 9 l l llllq 8 e t i r w d a o l 2 1 l b t 4 9 2 5 e l c y cs s e r d d a/ r w / v d a d l e c ) 2 ( n e cw b x e o o / is t n e m m o c na 0 h l llxxx p u t e s t e e m l o r t n o c d n a s s e r d d a 1 + n x x x xlxxx d i l a v p u t e s k c o l c 2 + n x x x xxxlq 0 a s s e r d d a f o s t n e t n o c 0 t u o d a e r 3 1 l b t 4 9 2 5
6.42 10 idt71v2546, 128k x 36, 3.3v synchronous zbt? sram with 2.5v i/o, burst counter, and pipelined outputs commercial and industria l temperature ranges burst write operation (1) burst read operation (1) write operation (1) notes: 1. h = high; l = low; x = don?t care; z = high impedance.. 2. ce = l is defined as ce 1 = l, ce 2 = l and ce 2 = h. ce = h is defined as ce 1 = h, ce 2 = h or ce 2 = l. notes: 1. h = high; l = low; x = don?t care; z = high impedance. 2. ce = l is defined as ce 1 = l, ce 2 = l and ce 2 = h. ce = h is defined as ce 1 = h, ce 2 = h or ce 2 = l. notes: 1. h = high; l = low; x = don?t care; ? = don?t know; z = high impedance. 2. ce = l is defined as ce 1 = l, ce 2 = l and ce 2 = h. ce = h is defined as ce 1 = h, ce 2 = h or ce 2 = l. e l c y cs s e r d d a/ r w / v d a d l e c ) 2 ( n e cw b x e o o / is t n e m m o c na 0 h l llxxx p u t e s t e e m l o r t n o c d n a s s e r d d a 1 + n x x h xlxxx r e t n u o c e c n a v d a , d i l a v p u t e s k c o l c 2 + n x x h xlxlq 0 a s s e r d d a 0 t n u o c . c n i , t u o d a e r 3 + n x x h xlxlq 1 + 0 a s s e r d d a 1 + 0 t n u o c . c n i , t u o d a e r 4 + n x x h xlxlq 2 + 0 a s s e r d d a 2 + 0 t n u o c . c n i , t u o d a e r 5 + na 1 hl llxlq 3 + 0 a s s e r d d a 3 + 0 a d a o l , t u o d a e r 1 6 + n x x h xlxlq 0 a s s e r d d a 0 t n u o c . c n i , t u o d a e r 7 + n x x h xlxlq 1 a s s e r d d a 1 t n u o c . c n i , t u o d a e r 8 + na 2 hl llxlq 1 + 1 a s s e r d d a 1 + 1 a d a o l , t u o d a e r 2 4 1 l b t 4 9 2 5 e l c y cs s e r d d a/ r w / v d a d l e c ) 2 ( n e cw b x e o o / is t n e m m o c na 0 l l lllxx p u t e s t e e m l o r t n o c d n a s s e r d d a 1 + n x x x xlxxx d i l a v p u t e s k c o l c 2 + nxxxxlxxd 0 a s s e r d d a o t e t i r w 0 5 1 l b t 4 9 2 5 e l c y cs s e r d d a/ r w / v d a d l e c ) 2 ( n e cw b x e o o / is t n e m m o c na 0 l l lllxx p u t e s t e e m l o r t n o c d n a s s e r d d a 1 + nxxhxllxx t n u o c . c n i , d i l a v p u t e s k c o l c 2 + nxxhxllxd 0 s s e r d d aa 0 t n u o c . c n i , e t i r w 3 + nxxhxllxd 1 + 0 a s s e r d d a 1 + 0 t n u o c . c n i , e t i r w 4 + nxxhxllxd 2 + 0 a s s e r d d a 2 + 0 t n u o c . c n i , e t i r w 5 + n1 a l l lllxd 3 + 0 a s s e r d d a 3 + 0 d a o l , e t i r wa 1 6 + nxxhxllxd 0 a s s e r d d a 0 t n u o c . c n i , e t i r w 7 + nxxhxllxd 1 a s s e r d d a 1 t n u o c . c n i , e t i r w 8 + na 2 l l lllxd 1 + 1 a s s e r d d a 1 + 1 a d a o l , e t i r w 2 6 1 l b t 4 9 2 5
6.42 idt71v2546 128k x 36, 3.3v synchronous zbt? sram with 2.5v i/o, burst counter, and pipelined outputs commercial and industri al temperature ranges 11 read operation with clock enable used (1) write operation with clock enable used (1) notes: 1. h = high; l = low; x = don?t care; z = high impedance. 2. ce = l is defined as ce 1 = l, ce 2 = l and ce 2 = h. ce = h is defined as ce 1 = h, ce 2 = h or ce 2 = l. notes: 1. h = high; l = low; x = don?t care; z = high impedance. 2. ce = l is defined as ce 1 = l, ce 2 = l and ce 2 = h. ce = h is defined as ce 1 = h, ce 2 = h or ce 2 = l. e l c y cs s e r d d a/ r w / v d a d l e c ) 2 ( n e cw b x e o o / is t n e m m o c na 0 h l llxxx p u t e s t e e m l o r t n o c d n a s s e r d d a 1 + n x x x xhxxx d e r o n g i 1 + n k c o l c 2 + na 1 h l llxxx d i l a v k c o l c 3 + nxxxxhxlq 0 q a t a d . d e r o n g i k c o l c 0 . s u b e h t n o s i 4 + nxxxxhxlq 0 q a t a d . d e r o n g i k c o l c 0 . s u b e h t n o s i 5 + na 2 hl llxlq 0 a s s e r d d a 0 ) . s n a r t s u b ( t u o d a e r 6 + na 3 hl llxlq 1 a s s e r d d a 1 ) . s n a r t s u b ( t u o d a e r 7 + na 4 hl llxlq 2 a s s e r d d a 2 ) . s n a r t s u b ( t u o d a e r 7 1 l b t 4 9 2 5 e l c y cs s e r d d a/ r w / v d a d l e c ) 2 ( n e cw b x e o o / is t n e m m o c na 0 l l lllxx . p u t e s t e e m l o r t n o c d n a s s e r d d a 1 + n x x x xhxxx . d e r o n g i 1 + n k c o l c 2 + na 1 l l lllxx . d i l a v k c o l c 3 + n x x x xhxxx . d e r o n g i k c o l c 4 + n x x x xhxxx . d e r o n g i k c o l c 5 + na 2 l l lllxd 0 d a t a d e t i r w 0 6 + na 3 l l lllxd 1 d a t a d e t i r w 1 7 + na 4 l l lllxd 2 d a t a d e t i r w 2 8 1 l b t 4 9 2 5
6.42 12 idt71v2546, 128k x 36, 3.3v synchronous zbt? sram with 2.5v i/o, burst counter, and pipelined outputs commercial and industria l temperature ranges notes: 1. h = high; l = low; x = don?t care; ? = don?t know; z = high impedance. 2. ce = l is defined as ce 1 = l, ce 2 = l and ce 2 = h. ce = h is defined as ce 1 = h, ce 2 = h or ce 2 = l. 3. device outputs are ensured to be in high-z after the first rising edge of clock upon power-up. read operation with chip enable used (1) write operation with chip enable used (1) notes: 1. h = high; l = low; x = don?t care; ? = don?t know; z = high impedance. 2. ce = l is defined as ce 1 = l, ce 2 = l and ce 2 = h. ce = h is defined as ce 1 = h, ce 2 = h or ce 2 = l. 3. device outputs are ensured to be in high-z after the first rising edge of clock upon power-up. e l c y cs s e r d d a/ r w / v d a d l e c ) 2 ( n e cw b x e o o / i ) 3 ( s t n e m m o c nxxlhlxx? . d e t c e l e s e d 1 + nxxlhlxx? . d e t c e l e s e d 2 + na 0 hl llxxz p u t e s t e e m l o r t n o c d n a s s e r d d a 3 + nxxlhlxxz . p o t s r o d e t c e l e s e d 4 + na 1 hl llxlq 0 a s s e r d d a 0 a d a o l . t u o d a e r 1 . 5 + nxxlhlxxz . p o t s r o d e t c e l e s e d 6 + nxxlhlxlq 1 a s s e r d d a 1 . d e t c e l e s e d . t u o d a e r 7 + na 2 hl llxxz . p u t e s t e e m l o r t n o c d n a s s e r d d a 8 + nxxlhlxxz . p o t s r o d e t c e l e s e d 9 + nxxlhlxlq 2 a s s e r d d a 2 . d e t c e l e s e d . t u o d a e r 9 1 l b t 4 9 2 5 e l c y cs s e r d d a/ r w / v d a d l e c ) 2 ( n e cw b x e o o / i ) 3 ( s t n e m m o c nxxlhlxx? . d e t c e l e s e d 1 + nxxlhlxx? . d e t c e l e s e d 2 + na 0 l l lllxz p u t e s t e e m l o r t n o c d n a s s e r d d a 3 + nxxlhlxxz . p o t s r o d e t c e l e s e d 4 + na 1 l l lllxd 0 d s s e r d d a 0 a d a o l . n i e t i r w 1 . 5 + nxxlhlxxz . p o t s r o d e t c e l e s e d 6 + nxxlhlxxd 1 d s s e r d d a 1 . d e t c e l e s e d . n i e t i r w 7 + na 2 l l lllxz . p u t e s t e e m l o r t n o c d n a s s e r d d a 8 + nxxlhlxxz . p o t s r o d e t c e l e s e d 9 + nxxlhlxxd 2 d s s e r d d a 2 . d e t c e l e s e d . n i e t i r w 0 2 l b t 4 9 2 5
6.42 idt71v2546 128k x 36, 3.3v synchronous zbt? sram with 2.5v i/o, burst counter, and pipelined outputs commercial and industri al temperature ranges 13 dc electrical characteristics over the operating temperature and supply voltage range (v dd = 3.3v5%) figure 2. lumped capacitive load, typical derating ac test conditions (v ddq = 2.5v) dc electrical characteristics over the operating temperature supply voltage range (1) (v dd = 3.3v5%) figure 1. ac test load ac test loads note: 1. the lbo, tms, tdi, tck and trst pins will be internally pulled to v dd and zz will be internally pulled to v ss if it is not actively driven in the application. notes: 1. all values are maximum guaranteed values. 2. at f = f max, inputs are cycling at the maximum frequency of read cycles of 1/t cyc ; f=0 means no input lines are changing. 3. for i/os v hd = v ddq ? 0.2v, v ld = 0.2v. for other inputs v hd = v dd ? 0.2v, v ld = 0.2v. v ddq /2 50 ? i/o z 0 = 50 ? 5294 drw 04 , l o b m y sr e t e m a r a ps n o i t i d n o c t s e t. n i m. x a mt i n u i | li |t n e r r u c e g a k a e l t u p n iv d d v , . x a m = n i v o t v 0 = d d _ _ _ 5a i | i l | z z d n a g a t j , o b lt n e r r u c e g a k a e l t u p n i ) 1 ( v d d v , . x a m = n i v o t v 0 = d d _ _ _ 0 3a i | o l |t n e r r u c e g a k a e l t u p t u ov t u o v o t v 0 = q d d d e t c e l e s e d e c i v e d , _ _ _ 5a v l o e g a t l o v w o l t u p t u oi l o v , a m 6 + = d d . n i m = _ _ _ 4 . 0v v h o e g a t l o v h g i h t u p t u oi h o v , a m 6 - = d d . n i m =0 . 2 _ _ _ v 1 2 l b t 4 9 2 5 s l e v e l e s l u p t u p n i s e m i t l l a f / e s i r t u p n i s l e v e l e c n e r e f e r g n i m i t t u p n i s l e v e l e c n e r e f e r g n i m i t t u p t u o d a o l t s e t c a v 5 . 2 o t 0 s n 2 v ( q d d ) 2 / v ( q d d ) 2 / 1 e r u g i f e e s 3 2 l b t 4 9 2 5 1 2 3 4 20 30 50 100 200 ? t cd (ty pi cal , ns ) capaci t ance (pf ) 80 5 6 5294 dr w05 l o b m y sr e t e m a r a ps n o i t i d n o c t s e t z h m 0 5 1z h m 3 3 1z h m 0 0 1 t i n u l ' m o cl ' d n il ' m o cl ' d n il ' m o cl ' d n i i d d r e w o p g n i t a r e p o t n e r r u c y l p p u s , n e p o s t u p t u o , d e t c e l e s e c i v e d / v d a d l v , x = d d , . x a m = v n i > v h i r o< v l i f = f , x a m ) 2 ( 5 2 35 3 30 0 30 1 30 5 20 6 2a m i 1 b s r e w o p y b d n a t s s o m c t n e r r u c y l p p u s , n e p o s t u p t u o , d e t c e l e s e d e c i v e d v d d v , . x a m = n i > v d h r o< v d l , 0 = f ) 3 , 2 ( 0 45 40 45 40 45 4a m i 2 b s r e w o p g n i n n u r k c o l c t n e r r u c y l p p u s , n e p o s t u p t u o , d e t c e l e s e d e c i v e d v d d v , . x a m = n i > v d h v < r o d l , f = f x a m ) 3 . 2 ( 0 2 10 3 10 1 10 2 10 0 10 1 1a m i 3 b s r e w o p e l d i t n e r r u c y l p p u s , n e p o s t u p t u o , d e t c e l e s e c i v e d n e c > v h i v , d d , . x a m = v n i > v d h r o< v d l f = f , x a m ) 3 , 2 ( 0 45 40 45 40 45 4a m 2 2 l b t 4 9 2 5
6.42 14 idt71v2546, 128k x 36, 3.3v synchronous zbt? sram with 2.5v i/o, burst counter, and pipelined outputs commercial and industria l temperature ranges ac electrical characteristics (v dd = 3.3v5%, commercial and industrial temperature ranges) notes: 1. t f = 1/t cyc . 2. measured as high above 0.6v ddq and low below 0.4v ddq . 3. transition is measured 200mv from steady-state. 4. these parameters are guaranteed with the ac load (figure 1) by device characterization. they are not production tested. 5. to avoid bus contention, the output buffers are designed such that t chz (device turn-off) is about 1ns faster than t clz (device turn-on) at a given temperature and voltage. the specs as shown do not imply bus contention because t clz is a min. parameter that is worse case at totally different test conditions (0 deg. c, 3.465v) than t chz , which is a max. parameter (worse case at 70 deg. c, 3.135v). z h m 0 5 1z h m 3 3 1z h m 0 0 1 l o b m y sr e t e m a r a p. n i m. x a m. n i m. x a m. n i m. x a mt i n u t c y c e m i t e l c y c k c o l c7 . 6 _ _ _ _ 5 . 7 _ _ _ _ 0 1 _ _ _ _ s n t f ) 1 ( e c n e u q e r f k c o l c _ _ _ _ 0 5 1 _ _ _ _ 3 3 1 _ _ _ _ 0 0 1z h m t h c ) 2 ( h t d i w e s l u p h g i h k c o l c0 . 2 _ _ _ _ 2 . 2 _ _ _ _ 2 . 3 _ _ _ _ s n t l c ) 2 ( h t d i w e s l u p w o l k c o l c0 . 2 _ _ _ _ 2 . 2 _ _ _ _ 2 . 3 _ _ _ _ s n s r e t e m a r a p t u p t u o t d c a t a d d i l a v o t h g i h k c o l c _ _ _ _ 8 . 3 _ _ _ _ 2 . 4 _ _ _ _ 5s n t c d c e g n a h c a t a d o t h g i h k c o l c5 . 1 _ _ _ _ 5 . 1 _ _ _ _ 5 . 1 _ _ _ _ s n t z l c ) 5 , 4 , 3 ( e v i t c a t u p t u o o t h g i h k c o l c5 . 1 _ _ _ _ 5 . 1 _ _ _ _ 5 . 1 _ _ _ _ s n t z h c ) 5 , 4 , 3 ( z - h g i h a t a d o t h g i h k c o l c5 . 13 5 . 13 5 . 13 . 3s n t e o e m i t s s e c c a e l b a n e t u p t u o _ _ _ _ 8 . 3 _ _ _ _ 2 . 4 _ _ _ _ 5s n t z l o ) 4 , 3 ( e v i t c a a t a d o t w o l e l b a n e t u p t u o0 _ _ _ _ 0 _ _ _ _ 0 _ _ _ _ s n t z h o ) 4 , 3 ( z - h g i h a t a d o t h g i h e l b a n e t u p t u o _ _ _ _ 8 . 3 _ _ _ _ 2 . 4 _ _ _ _ 5s n s e m i t p u t e s t e s e m i t p u t e s e l b a n e k c o l c5 . 1 _ _ _ _ 7 . 1 _ _ _ _ 0 . 2 _ _ _ _ s n t a s e m i t p u t e s s s e r d d a5 . 1 _ _ _ _ 7 . 1 _ _ _ _ 0 . 2 _ _ _ _ s n t d s e m i t p u t e s n i a t a d5 . 1 _ _ _ _ 7 . 1 _ _ _ _ 0 . 2 _ _ _ _ s n t w s / r ( e t i r w / d a e r w e m i t p u t e s )5 . 1 _ _ _ _ 7 . 1 _ _ _ _ 0 . 2 _ _ _ _ s n t v d a s / v d a ( d a o l / e c n a v d a d l e m i t p u t e s )5 . 1 _ _ _ _ 7 . 1 _ _ _ _ 0 . 2 _ _ _ _ s n t c s e m i t p u t e s t c e l e s / e l b a n e p i h c5 . 1 _ _ _ _ 7 . 1 _ _ _ _ 0 . 2 _ _ _ _ s n t b s ( e l b a n e e t i r w e t y b w b e m i t p u t e s ) x5 . 1 _ _ _ _ 7 . 1 _ _ _ _ 0 . 2 _ _ _ _ s n s e m i t d l o h t e h e m i t d l o h e l b a n e k c o l c5 . 0 _ _ _ _ 5 . 0 _ _ _ _ 5 . 0 _ _ _ _ s n t a h e m i t d l o h s s e r d d a5 . 0 _ _ _ _ 5 . 0 _ _ _ _ 5 . 0 _ _ _ _ s n t d h e m i t d l o h n i a t a d5 . 0 _ _ _ _ 5 . 0 _ _ _ _ 5 . 0 _ _ _ _ s n t w h / r ( e t i r w / d a e r w e m i t d l o h )5 . 0 _ _ _ _ 5 . 0 _ _ _ _ 5 . 0 _ _ _ _ s n t v d a h / v d a ( d a o l / e c n a v d a d l e m i t d l o h )5 . 0 _ _ _ _ 5 . 0 _ _ _ _ 5 . 0 _ _ _ _ s n t c h e m i t d l o h t c e l e s / e l b a n e p i h c5 . 0 _ _ _ _ 5 . 0 _ _ _ _ 5 . 0 _ _ _ _ s n t b h ( e l b a n e e t i r w e t y b w b e m i t d l o h ) x5 . 0 _ _ _ _ 5 . 0 _ _ _ _ 5 . 0 _ _ _ _ s n 4 2 l b t 4 9 2 5
6.42 idt71v2546 128k x 36, 3.3v synchronous zbt? sram with 2.5v i/o, burst counter, and pipelined outputs commercial and industri al temperature ranges 15 timing waveform of read cycle (1,2,3,4) notes: 1. q (a 1 ) represents the first output from the external address a 1 . q (a 2 ) represents the first output from the external address a 2 ; q (a 2+1 ) represents the next output data in the burst sequence of the base address a 2 , etc. where address bits a0 and a1 are advancing for the four word burst in the sequence defined by the state of the lbo input. 2. ce 2 timing transitions are identical but inverted to the ce 1 and ce 2 signals. for example, when ce 1 and ce 2 are low on this waveform, ce 2 is high. 3. burst ends when new address and control are loaded into the sram by sampling adv/ ld low. 4. r/ w is don't care when the sram is bursting (adv/ ld sampled high). the nature of the burst access (read or write) is fixed by the state of the r/ w signal when new address and control are loaded into the sram. adv/ ld ( cen high, eliminates current l-h clock edge) o2(a2) t cd t hadv pipeline read (burst wraps around to initial state) t cdc t clz t chz t cd t cdc r/ w clk cen address oe data out t he t se a1 a2 o1(a2) t ch t cl t cyc t sadv t hw t sw t ha t sa t hc t sc burst pipeline read pipeline read bw 1 - bw 4 5294 drw 06 ce 1 , ce 2 (2) q(a 2+3 ) q(a 2 ) q(a 2+2 ) q(a 2+2 ) q(a 2+1 ) q(a 2 ) q(a 1 ) ,
6.42 16 idt71v2546, 128k x 36, 3.3v synchronous zbt? sram with 2.5v i/o, burst counter, and pipelined outputs commercial and industria l temperature ranges notes: 1. d (a 1 ) represents the first input to the external address a 1 . d (a 2 ) represents the first input to the external address a 2 ; d (a 2+1 ) represents the next input data in the burst sequence of the base address a 2 , etc. where address bits a 0 and a 1 are advancing for the four word burst in the sequence defined by the state of the lbo input. 2. ce 2 timing transitions are identical but inverted to the ce 1 and ce 2 signals. for example, when ce 1 and ce 2 are low on this waveform, ce2 is high. 3. burst ends when new address and control are loaded into the sram by sampling adv/ ld low. 4. r/ w is don't care when the sram is bursting (adv/ ld sampled high). the nature of the burst access (read or write) is fixed by the state of the r/ w signal when new address and control are loaded into the sram. 5. individual byte write signals ( bw x) must be valid on all write and burst-write cycles. a write cycle is initiated when r/ w signal is sampled low. the byte write information comes in two cycles before the actual data is presented to the sram. timing waveform of write cycles (1,2,3,4,5) t he t se r / w a 1 a 2 clk c e n adv/ l d address o e data in t hd t sd t ch t cl t cyc t hadv t sadv t hw t sw t ha t sa t hc t sc burst pipeline write pipeline write pipeline write t hb t sb (burst wraps around to initial state) t hd t sd ( cen high, eliminates current l-h clock edge) (2) d( a2+2 ) d( a2+3 ) d(a 1 ) d(a 2 ) d(a 2 ) 5294 drw 07 b w 1 - b w 4 c e 1, c e 2 d(a 2+1 )
6.42 idt71v2546 128k x 36, 3.3v synchronous zbt? sram with 2.5v i/o, burst counter, and pipelined outputs commercial and industri al temperature ranges 17 t he t se r/ w a 1 a 2 clk cen adv/ ld address ce 1 , ce 2 (2) bw 1 - bw 4 data out q(a 3 ) q(a 1 ) q(a 6 ) q(a 7 ) t cd read t chz 5294 drw 08 write t clz d(a 2 ) d(a 4 ) t cdc d(a 5 ) write t ch t cl t cyc t hw t sw t ha t sa a 4 a 3 t hc t sc t sd t hd t hadv t sadv a 6 a 7 a 8 a 5 a 9 data in t hb t sb oe read read notes: 1. q (a 1 ) represents the first output from the external address a 1 . d (a 2 ) represents the input data to the sram corresponding to address a 2 . 2. ce 2 timing transitions are identical but inverted to the ce 1 and ce 2 signals. for example, when ce 1 and ce 2 are low on this waveform, ce 2 is high. 3. individual byte write signals ( bw x) must be valid on all write and burst-write cycles. a write cycle is initiated when r/ w signal is sampled low. the byte write information comes in two cycles before the actual data is presented to the sram. timing waveform of combined read and write cycles (1,2,3)
6.42 18 idt71v2546, 128k x 36, 3.3v synchronous zbt? sram with 2.5v i/o, burst counter, and pipelined outputs commercial and industria l temperature ranges notes: 1. q (a 1 ) represents the first output from the external address a 1 . d (a 2 ) represents the input data to the sram corresponding to address a 2 . 2. ce 2 timing transitions are identical but inverted to the ce 1 and ce 2 signals. for example, when ce 1 and ce 2 are low on this waveform, ce 2 is high. 3. cen when sampled high on the rising edge of clock will block that l-h transition of the clock from propogating into the sram. the part will behave as if the l-h clock transition did not occur. all internal registers in the sram will retain their previous state. 4. individual byte write signals ( bw x) must be valid on all write and burst-write cycles. a write cycle is initiated when r/ w signal is sampled low. the byte write information comes in two cycles before the actual data is presented to the sram. timing waveform of cen operation (1,2,3,4) t he t se r/ w a 1 a 2 clk c e n adv/ l d address b w 1 - b w 4 o e data out q(a 3 ) t cd t clz t chz t ch t cl t cyc t hc t sc d(a 2 ) t sd t hd t cdc a 4 a 5 t hadv tsadv t hw t sw t ha t sa a 3 t hb t sb data in q(a 1 ) 5294 drw 09 q(a 1 ) b(a 2 ) c e 1 , c e 2 (2) ,
6.42 idt71v2546 128k x 36, 3.3v synchronous zbt? sram with 2.5v i/o, burst counter, and pipelined outputs commercial and industri al temperature ranges 19 timing waveform of cs operation (1,2,3,4) notes: 1. q (a 1 ) represents the first output from the external address a 1 . d (a 3 ) represents the input data to the sram corresponding to address a 3 . 2. ce 2 timing transitions are identical but inverted to the ce 1 and ce 2 signals. for example, when ce 1 and ce 2 are low on this waveform, ce 2 is high. 3. cen when sampled high on the rising edge of clock will block that l-h transition of the clock from propogating into the sram. the part will behave as if the l-h clock transition did not occur. all internal registers in the sram will retain their previous state. 4. individual byte write signals ( bw x) must be valid on all write and burst-write cycles. a write cycle is initiated when r/ w signal is sampled low. the byte write information comes in two cycles before the actual data is presented to the sram. r/ w a1 clk adv/ l d address o e data out q(a 1 ) t cd t clz t chz t cdc t ch t cl t hc t sc t sd t hd a 5 a 3 t sb data in t he t se a 2 t ha t sa a 4 t hw t sw t hb c e n t hadv t sadv 5294 drw 10 q(a 2 ) q(a 4 ) d(a 3 ) b w 1 - b w 4 c e 1, c e 2 (2) ,
6.42 20 idt71v2546, 128k x 36, 3.3v synchronous zbt? sram with 2.5v i/o, burst counter, and pipelined outputs commercial and industria l temperature ranges timing waveform of oe operation (1) note: 1. a read operation is assumed to be in progress. ordering information oe data out t ohz t olz t oe valid 5294 drw 11 100-pin plastic thin quad flatpack (tqfp) 119 ball grid array (bga) power xx speed xx package pf bg xxxx 150 133 100 clock frequency in megahertz 5294 drw 12 device type 71v2546 128kx36 pipelined zbt sram with 2.5v i/o x process/ temperature range blank 8 tube or tray tape and reel xx s standard power x blank x first generation or current die step current generation die step optional blank i commercial (0c to +70c) industrial (-40c to +85c) g green x x
6.42 idt71v2546 128k x 36, 3.3v synchronous zbt? sram with 2.5v i/o, burst counter, and pipelined outputs commercial and industri al temperature ranges 21 idt and the idt logo is a registered trademark of integrated device technology, inc. datasheet document history 12/31/99 created preliminary datasheet from 71v2556 and 71v2558 datasheets. changed t cdc , t clz , and t chz minimums from 1.0ns to 1.5ns. 03/04/00 pg. 1,14,15,22 add 150 mhz speed grade offering 05/02/00 pg. 5,6 insert clarification note to recommended operating temperature and absolute max ratings tables pg. 5,6,7 clarify note on tqfp and bga pin configurations; corrected typo in pinout pg. 6 add bga capacitance table pg. 21 add 100 pin tqfp package diagram outline 05/26/00 pg. 23 add new package offering, 13 x 15mm 165 fbga correct 119 bga package diagram outline 07/26/00 pg. 5-8 add zz, sleep mode reference note to bg119, pk100 and bq165 pinouts pg. 8 update bq165 pinout pg. 23 update bg119 package diagram outline dimensions 10/25/00 remove preliminary status from datasheet pg. 8 add reference note to pin n5 on bq165, reserved for jtag pin trst 05/20/02 pg. 1-8,15,22,23,27 added jtag "sa" version functionality and updated zz pin descriptions and notes 09/30/04 pg. 7 updated pin configuration for the 119 bga-reordered i/o signals on p6, p7 (128k x 36) and p7, n6, l6, k7, h6, g7, f6, e7, d6 (256k x 18). 02/23/07 pg. 27 added x step die generation to data sheet ordering information. 05/27/10 pg. 24 added "restricted hazardous substance device" to the ordering information. 04/11/11 pg. 1-21 removed 71v2548 (eol), fbga 165 pin, and jtag information. pg. 13 added 150mhz data for industrial information. pg. 20 added tape and reel to ordering information and updated description of restricted hazardous substance device to green. zbt and zerobus turnaround are trademarks of integrated device technology, inc. and the architecture is supported by micron tec hnology and motorola inc. corporate headquarters for sales: 6024 silver creek valley rd 800-345-7015 or 408-284-8200 san jose, ca 95138 fax: 408-284-2775 www.idt.com for tech support: sramhelp@idt.com 408-284-4532

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